In general, in the case that memory cells in a DRAM consist of N-channel MOS transistors for driving and capacitors for storage, to store a full potential of a power source to a storage node, a signal having a potential which is larger than the potential of the power source by at least a threshold voltage of the N-channel MOS transistor should be transmitted to the storage node.
In a prior would line driving circuit using N-channel MOS transistors, because only N-channel MOS transistors are used, a decrease in area can be achieved. Also, there is no LATCH-UP problem and improved driving speed can be obtained relative to the case that P-channel MOS transistors are used. However, as shown in FIG. 2 illustrating waveforms useful in explaining the operation of the circuit of FIG. 1, it is disadvantageous that a maximum voltage at node 3 is too high. Also, competition between piecharge of the node 3 and rising of select signals Sxn gives rise to trouble. In general, the potential at the node 3 rises up to a potential much higher than power source voltage Vcc by bootstraping operations in twice (presently, in case of 4M DRAM, when Vcc is 5V, maximum voltage at node 3 becomes about 11V.). Therefore, it is difficult to obtain a P-N junction with high reliability at node 3.
In a prior word line driving circuit using CMOS transistors as shown in FIG. 3, an additional driving voltage source Vpp much higher than power source Vcc by at least threshold voltage of the N-channel MOS transistor is used. In the circuit of FIG. 3, it is disadvantageous that, relative to the circuit using N-channel MOS transistors, it is difficult to achieve area reduction and its driving capability degrades. But, it is advantageous that even though a device is shrunk continuously, high reliability of the device can be maintained. Also, because a bootstraping operation is not used, there is no problem related to competition between the precharge at node 14 and the rising of select signals Sxn.
However, because a HOLD-OFF function of maintaining unselected word lines at ground potential (i.e. 0V) against coupling noises is performed by connecting the unselected word lines through a P-channel MOS transistor MP11 to select signal Sxn having ground potential 0V, a voltage at common gate electrode of transistors MP11 and MP12, i.e. at node 14, equals to 0V, and also the potential of the unselect signal Sxn becomes 0V. Therefore, because, during an interval from 0V to the absolute value of the threshold voltage Vtp, the transistor MP11 is ruined-off, these would lines become in OFF state. Thus, it is disadvantageous that an additional HOLD-OFF circuit is required.